[Info-vax] nice for VMS

[Jan-Erik Söderholm]

Arne Vajhøj wrote:
> John Reagan wrote:
>> "Arne Vajhøj" <arne at vajhoej.dk> wrote in message 
>> news:49e28914$0$90266$14726298 at news.sunsite.dk...
>>> Most HLL compiler allow you to specify that data should not be
>>> natural aligned. And take the performance hit, which even at older
>>> Alphas could be >x10.
>>
>> We have no such feature.  Unless you lie to the compiler, we should 
>> never generate code that gets an alignment fault on either Alpha or 
>> Itanium.
>>
>> - If the compiler knows that the field is aligned, we'll generate a 
>> single LDL/LDQ instruction.
>>
>> - If the compiler knows (or thinks) the field is unaligned (ie, you 
>> used #pragma nomember_alignment or the equivalent in the language - 
>> some languages like COBOL/BASIC default to byte-aligned packing like 
>> VAX), then the compiler will generate multiple instructions to 
>> fetch/store the data in pieces to avoid the alignment fault.
>>
>> Same for Itanium.
>>
>> The common place to get alignment faults are mostly pointer 
>> dereferences.  C will assume that a pointer to an int is a pointer to 
>> an ALIGNED int.  So if you take the address of some random byte in a 
>> buffer and pass that pointer to some code to start filling in the 
>> buffer, you'll get alignment faults. There are pragmas to tell the 
>> compiler that the destination is no aligned and to generate the 
>> multi-instruction sequence.
>>
>> Again, same for Itanium.
>>
>> So in summary, asking for VAX-style packing on byte boundaries should 
>> not generate alignment faults.  Now, it isn't as fast as aligned code 
>> since you'll execute perhaps 6-8 instructions for the unaligned form 
>> vs 1 instruction for the aligned form.
> 
> I were talking about /NOMEMBER_ALIGNMENT.
> 
> I was not aware of that you actually had the compiler generate special
> code to get non aligned data instead of having the CPU do it.
> 
> Interesting that a software solution is faster than a hardware
> solution.
> 
> I assume that is because the unaligned access is treated more
> like a fault and completely messes up the pipeline, while the generated
> instructions keeps the pipeline flowing.

On Alpha it was (is) PAL code that "fixes" the unaligned error,
on Itanium the processors interrupts VMS and the VMS executive
has to fix it (which is very much slower). One presentation gave
the range 20 to 100 times slower on IA64 then on Alpha. Another
presentation said that if you have 100.000 faults per seconds
it should be fixed. 10.000 faults per seconds could be a problem
on a heavily loaded system, otherwise probably not (both on
typical IA64 systems).


> 
> When I did my test (15 years ago) I most likely did "lie" to the
> compiler.
> 
> Arne