[Info-vax] OT: IBM Offering $9-10 Per Share for Sun

[johnwallace4 at yahoo.co.uk]

On Apr 14, 11:30 pm, johnwalla... at yahoo.co.uk wrote:
> On Apr 14, 10:08 pm, Keith Parris <keithparris_nos... at yahoo.com>
> wrote:
>
>
>
> > Arne Vajhøj wrote:
> > > JF Mezei wrote:
> > >> Not necesaarily. Consider NSK under Compaq/Pfeiffer where he undertook
> > >> to port NSK to Alpha. NSK had special features that required "lockstep"
> > >> which was a feature that needed to be added to Alpha (scheduled to come
> > >> with EV7, not sure if they bothered).
> > ...
> > > NSK in it current way of doing things has some special
> > > hardware requirements.
> > ...
> > > And even how NSK works could be changed if HP decided to.
>
> > (Probably because Lockstepping started to interfere with processor
> > performance) NSK changed course for Itanium and no longer requires
> > Lockstep -- they took a different approach called NonStop Advanced
> > Architecture (NSAA) where instead of having two pairs of lock-stepped
> > processors, they instead compare the outputs of 3 processors. Cheaper,
> > faster, and can use mainstream processors. Seehttp://h20223.www2.hp.com/NonStopComputing/cache/77119-0-0-0-121.html
>
> That's interesting. I'd always wondered how "lockstep" (whatever it
> actually meant) on Alpha would cope with the kind of "soft errors" you
> are likely to see from time to time in modern systems - a routine
> cache miss on one processor but not on its other half needn't
> necessarily be fatal, but on a trivial level would result in loss of
> exact synchronisation between the two processors.
>
> Perhaps you can point to a paper with a more detailed description of
> what "lockstep" has traditionally meant? The one I've just checked,
> "Fault Tolerance in Tandem Computer Systems" [1] goes back before
> "mainstream" MIPS RISC chips came into the Tandem family, and seems to
> state that the processor chips themselves weren't necessarily in
> lockstep, only their interactions with the IO bus needed to be in sync
> (eg page 6, 3rd paragraph), because this simplifies the error
> detection problem. That architecture would also seemingly have
> eliminated any need for two MIPS chips to be in lockstep (and, by the
> same logic, eliminates the need for two EV7 chips to be in lockstep)
> by using software and a reliable message passing IO bus to make sure
> that *the software's view of the system* consistently survives any
> single hardware or software failure.
>
> When you said "can use mainstream processors", do you mean NonStop for
> AMD64 is on the way, or did mainstream get redefined yet again?
>
> [1]http://www.hpl.hp.com/techreports/tandem/TR-90.5.pdf

Bah humbug. "routine cache miss" should have been more like "routine
random soft uncorrectable cache error (which might typically just end
up being treated as a cache miss)". Sorry for the error.