[Info-vax] Itanium CPU configuration conundrum

[VAXman- at SendSpamHere.ORG]

In article <h86m71$i8b$1 at pcls6.std.com>, moroney at world.std.spaamtrap.com (Michael Moroney) writes:
>VAXman-  @SendSpamHere.ORG writes:
>
>>Two, supposedly, identical Integrity 6600s.  One, however, reports that it
>>has 4 sockets filled with quad core CPUs while the other claims 4 sockets 
>>with dual core CPUs.  
>
>>HP says they don't have quad cores.  Strangely, VMS fires up and it says
>>that it is starting CPUs #1 through #15.  Is its console and what it is
>>reporting to VMS horked?
>
>The Itanium zx2 chipset has a duplicate set of registers that can enable
>it to switch between processes very quickly (by switching register sets).  
>VMS knows about this and implements it by treating the second register set
>as a second CPU, if some magic bit is set, making each core into two
>virtual CPUs.  So, a two core chip can appear as either two or 4 CPUs to
>VMS.  In reality, there are still two cores, and a given core may spend
>half its time as one CPU and half the time as the other CPU, so
>CPU-intensive jobs won't execute any faster.  There are probably some
>situations where enabling this can cause a speedup.  Supposedly the VMS
>scheduler has enough smarts to schedule two processes on different cores
>rather than the two virtual CPUs on one core if it can, as this is 
>obviously faster.
>
>I believe SHOW CPU/FULL will identify the virtual CPU pairs somehow.
>
>It appears that the magic bit got set on one 6600 and not the other.

And this "magic bit" is switched on and off how?  

The PAK is for 4 sockets and 8 units (CPUs), and thus is causing a 
%LICENSE-F-EXCEEDED, attempted usage exceeds active license limits

-- 
VAXman- A Bored Certified VMS Kernel Mode Hacker    VAXman(at)TMESIS(dot)ORG

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