[Info-vax] Itanium CPU configuration conundrum

[VAXman- at SendSpamHere.ORG]

In article <SpqdnTCEzeGKtjrXnZ2dnUVZ_rGdnZ2d at earthlink.com>, "John Reagan" <johnrreagan at earthlink.net> writes:
>
>"Michael Moroney" <moroney at world.std.spaamtrap.com> wrote in message 
>news:h86m71$i8b$1 at pcls6.std.com...
>>
>> The Itanium zx2 chipset has a duplicate set of registers that can enable
>> it to switch between processes very quickly (by switching register sets).
>> VMS knows about this and implements it by treating the second register set
>> as a second CPU, if some magic bit is set, making each core into two
>> virtual CPUs.  So, a two core chip can appear as either two or 4 CPUs to
>> VMS.  In reality, there are still two cores, and a given core may spend
>> half its time as one CPU and half the time as the other CPU, so
>> CPU-intensive jobs won't execute any faster.  There are probably some
>> situations where enabling this can cause a speedup.  Supposedly the VMS
>> scheduler has enough smarts to schedule two processes on different cores
>> rather than the two virtual CPUs on one core if it can, as this is
>> obviously faster.
>>
>
>Uh.... Has nothing to do with the chipset.  All a function of the 
>Montecito/Montvale Itanium chips.  Each core can have 2 threads (each with 
>its own register state).  The two threads share the cache and the functional 
>units so certain workloads can certainly thrash the caches.  The scheduler 
>will attempt not to schedule on a thread if there are other cores available. 
>Even with the 2 cores, they still share logic to get data on/off the socket.
>
>To see/check the status:
>
>$ mcr sys$test:hthreads

Thanks all.  The Integrity has been put on a low-silicon diet and has now 
lost the excess weight of 8 CPUs.

I've got the chance to toy with this box for a couple of more days before
it gets put into production.  It's a chance to check out some of my kernel
hacks on a multi-CPU IA64 box.
-- 
VAXman- A Bored Certified VMS Kernel Mode Hacker    VAXman(at)TMESIS(dot)ORG

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