[Info-vax] RealWorldTech on Poulson

[Neil Rieck]

On Jun 28, 4:13 pm, Keith Parris <keithparris_deletet... at yahoo.com>
wrote:
> Poulson: The Future of Itanium Servers
> By: David Kanter | 05-18-2011

http://www.realworldtech.com/page.cfm?ArticleID=RWT051811113343
>
David Kanter's first paragraph tells it like it is:
Itanium was originally conceived in the early 1990’s by the architects
and engineers who had worked on HP’s PA-RISC. Many of them were
convinced that dynamic instruction scheduling and out-of-order
execution would ultimately prove to be too complex and power hungry.
They believed that single threaded performance would not scale in the
future. It is certainly true that many of the circuits in out-of-order
designs can be power hungry - the re-order buffer, schedulers and
renaming logic are fairly complicated and do not scale well to very
large sizes. Instead of relying on extensive scheduling and renaming
logic, the architects from HP and Intel took a different approach –
embracing a VLIW (Very Long Instruction Word) philosophy. Itanium
pushed the instruction scheduling burden onto the compiler and
designed a number of ISA features that would assist software
scheduling. The hardware was intended to be extremely simple with
totally static scheduling. In theory, removing all the complicated
scheduling and out-of-order logic would reduce power and scale better
to smaller process nodes.

 ###

Personal Comment: We all know that CISC architectures were too
complicated to allow further development of computer technology. Then
researchers at IBM came up with RISC which allowed the development of
super scalar technologies like OOE. (many industry people, including
me, though the shift from CISC to RISC might be a mistake; but
academics looking at yearly progress charts (smaller, cheaper, faster)
in both memory and CPUs had the correct view. We've all seen the
instruction complexity chart showing "CISC on the left, EPIC in the
middle, and RISC on the right". Once HP engineers saw the speed-up
going from CISC to RISC (due to instruction simplicity) then how did
they ever think a mid point like EPIC would ever be as fast as RISC?

see this chart: http://www3.sympatico.ca/n.rieck/docs/alpha_diary.html#vax_vs_alpha
(yep, that jump in the middle is an order-of-magnitude jump; also
notice that the RISC slope rises faster than CISC)

NSR