[Info-vax] RealWorldTech on Poulson

[Neil Rieck]

>
> Admitting that EPIC did not pan out is one thing.  But transforming an
> EPIC architecture into an OOE one is another.
>
As I understand the current debacle, EPIC relied on advances in
complier technology which never occurred. Any speed improvements we
saw in Itanium where the result of other technological improvements
like DDR3 and geometry shrink which would have eventually made their
way onto Alpha platforms had the HPQ suits not interfered with
engineering. IMHO, if Intel began nudging Itanium away from EPIC (but
in the direction of super scaler RISC), the changes could be
implemented in the GEM back-end code generators (it would mean
generating Poulson-specific code but we have seen DEC compliers do
this already in Alpha and Itanium). For example, here are some tuning
alternatives for the DEC-C compiler:

http://h71000.www7.hp.com/commercial/c/docs/5492profile_005.html#index_x_146

$cc/optimize=tune=xxx

where xxx can be one of:
GENERIC
EV4 - Selects instruction tuning for the 21064, 21064A, 21066, and
21068
EV5 - Selects instruction tuning for the 21164 implementation of the
Alpha architecture.
EV56 - Selects instruction tuning for the 21164 chip
PCA56 - Selects instruction tuning for the 21164PC
EV6 - Selects instruction tuning for the first-generation 21264
implementation of the Alpha architecture.
EV67 - Selects instruction tuning for the second-generation 21264
implementation of the Alpha architecture.
ITANIUM2

###

Personal comment: I think Intel and HP are currently at a critical
point where the next few decisions will allow the Itanium program to
"take flight and dominate the enterprise  market" or crash. As far as
Intel is concerned, they make products for all markets so the death of
Itanium would not take them down. As far as HP is concerned, PA-RISC
and Alpha are gone so the death of Itanium would hurt them. EPIC never
worked as expected but "super-scaler RISC" did so both companies would
be wise to shift Itanium in that direction.

NSR