[Info-vax] In memoriam: 10 years since Alpha's passing away.

[Johnny Billquist]

On 2011-07-06 23.20, glen herrmannsfeldt wrote:
> Johnny Billquist<bqt at softjar.se>  wrote:
>> On 2011-07-06 15.39, Bob Koehler wrote:
>>> Hans Vlems<hvlems at freenet.de>   writes:
>>>> The VAX was a _true_ 32 bit architecture, right?
>
>>>      The original VAX hardware architecture was spec'ed to match the 30
>>>      bit SBI on the 11/780.  For a long time VAXen had 30 bit or narrower
>>>      busses.  Although laid out as a 32 bit architecture in most ways, it
>>>      didn't become true 32 bit until an ECO to the spec several years later,
>>>      when VAXen were designed with wider busses.
>
>> Not really, actually. The hardware address of the original VAX design is
>> actually only 30 bits. The page address register in the MMU have 21 bits
>> for the physical address, while the virtual address provides the 9 low
>> bits, which means you can never get more than 30 address bits from the
>> architecture.
>
> The virtual address space is (*) 32 bits, divided into three regions.

Well, technically it was four regions, although one (S1) was left 
unused, and pretty much unspecified.

> The upper half (31 bits) for the system region, the lower half split
> into P0 program region (30 bits) and P1 control region (30 bits).
> So, the per process (user) space can't be more than 2GB.

Right.

> PTEs, in the VAX Architecture as published in 1987, have a (V) Valid
> bit, a four bit (PROT) protection mode field, a (M) Modify bit,
> five reserved bits, and a 21 bit (PFN) page frame number.
>
> (snip)
>
>> This was eventually addressed in the NVAX, which added a second mode to
>> the MMU page address registers, where 4 previously unused/undefined bits
>> were added to the address part, making the actual physical address
>> formed to be 34 bits on the VAX. But that requires you to set up the MMU
>> in a different mode.
>
> According to the "VAX Architecture Reference Manual" four bits are
> reserved for software use, two marked as (OWN) owner, and one
> just reserved for DIGITAL, must be zero.

Yes. You need to read a newer version of the VARM. :-)
Check 
http://bitsavers.trailing-edge.com/pdf/dec/vax/archSpec/EL-00032-00-decStd32_Jan90.pdf, 
which is dated January 1990.

There are two defined formats for the PTE. You've seen one. The other 
have 25 bits for the PFN, one bit reserved for software, and the rest is 
the same.

Thus, you'll get either a 30 bit physical address, or a 34 bit physical 
address from the address translation. How that is mapped to different 
buses outside of the CPU is a different matter, which might force other 
restrictions.

	JOhnny