[Info-vax] VMS port to x86

[John Wallace]

On Mar 21, 7:32 pm, koeh... at eisner.nospam.encompasserve.org (Bob
Koehler) wrote:
> In article <jkcjcn$p3... at Iltempo.Update.UU.SE>, Johnny Billquist <b... at softjar.se> writes:
>
> > No, they don't.
>
>    Intel, not to mention every other reference I've seen, says they do:
>
> http://www.intel.com/Assets/en_US/PDF/manual/253668.pdf?wapkw=cpu+arc...
>
>    Intel. 64 and IA-32 Architectures
>    Software Developer.s Manual
>    Volume 3A:
>    System Programming Guide, Part 1
>
>    "The processor.s segment-protection mechanism recognizes 4 privilege
>     levels, numbered from 0 to 3."

There's a discussion for anyone interested to have about how well the
AMD64 and IA64 protection mechanisms map onto the VMS-required
mechanisms, and how exploit-proof they might be in reality. My
recollection is that Alpha only had two protection levels in the
hardware, the rest was implemented in PALcode, but the Alpha
architecture and design and the VMS implementation appeared reasonably
leakproof, subject to the occasional near-inevitable software bug.

x86 wasn't really architected, just thrown together over a number of
years. AMD64 and IA64 attempted to address that but who knows how
successful they were technically?

The increasing use of HYPErvisors on AMD64 and elsewhere may make IT
people increasingly conscious of things like unauthorised privilege
escalation and information leakage. Or may not.