[Info-vax] OT: Halt and Catch Fire

[terry+googleblog at tmk.com]

On Thursday, June 4, 2015 at 3:27:36 AM UTC-4, JohnF wrote:
> As pointed out, no model 69, though I do recall a 65. And I also
> recall that list posted on the front panel of either our 360/30 or 40.
> Let's see, it also had RSC=read and shred card, among maybe one or two
> dozen other mnemonics. But I don't have a copy.
> You think you could scan your copy and post a pdf somewheres???

Model 69 was probably part of the joke nature of the card that listed the HCF instruction.

I never had an IBM CPU burn. I had a bunch of ITT Courier pseudo-3277 controllers that tended to smolder. I told my students "What do you expect from a company that makes both atomic bomb parts and Twinkies?". The ITT service guy was NOT amused by my putting "Thank you for not smoking" desk signs on top of each of the controllers.

RSC is only implemented by the IBM 2560 MFCM (officially "MultiFunction Card Machine", but more commonly known as the "Mother-F****** Card Mangler") due to its 2 input hoppers, 5 output stackers, and the non-deterministic path between them, where a card might randomly encounter a read station, a punch station, or an interpretation station. The initial 90-degree turn and the subsequent 180-degree turn with rotation were added simply to frustrate the user or CE who attempted to determine where the 12-car[d] pileup had happened inside the machine. https://www.google.com/search?q=ibm+2560&tbm=isch

To briefly answer some later posts...

I'm pretty sure that it was called a "hard wait" state. Machine problems during IMPL didn't get that far (since there was no WAIT instruction loaded yet). There were a row of front lamps (top right by the "Emergency Pull", IIRC) with legends like "CPU EARLY", "CPU LATE", and my favorite, "SYSTEM DAMAGE". I had a 3125 (370/125) with an add-on memory cabinet from MAI (installed with a Sawzall and hundreds of wire-wrap wires coming out of the 3125 cabinet and into the memory cabinet), where if the add-on memory was powered on during IMPL, you got both a CPU EARLY and a CPU LATE. There was only a 30-second or so period to power it on, late in IMPL, so it would be detected and sized.

Microcoded CPUs generally don't have hardware-level HALT instructions - the microcode keeps spinning to detect changes in machine state and respond accordingly. Even microcoded systems with front panels had the front panel service routine (including single step) implemented in microcode.

For the ultimate reference to things IBMish, we'd need to tempt Lynn Wheeler to post here. http://www.garlic.com/~lynn/subtopic.html