[Info-vax] On the topic of Open Compute Designs Possibly Suitable for OpenVMS x86-64

[Stephen Hoffman]

On 2015-03-13 19:58:24 +0000, Simon Clubley said:

> That's exactly why I asked about ECC :-), as I had recently seen your 
> comp.risks entry before reading your c.o.v posting.

FWIW...
ECC might not be enough.
Some DDR3 and DDR4 is vulnerable to rowhammer, while other DDR3 and 
DDR4 memory — even that without ECC — does not appear to be.
Single bit error correction with double bit error detection ECC is 
still vulnerable to rowhammer when more than two bits are flipped, 
while higher-grade ECC appears not to be.
Recent Xeon processors do have memory refresh mechanisms that can 
mitigate rowhammer.
For those that want to test the local gear, memtest86 does now have a 
test for this.



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