[Info-vax] Notable VMS "feature"

[VAXman- at SendSpamHere.ORG]

In article <n89ec2$1bpl$1 at gioia.aioe.org>, George Cornelius <cornelius at charter.NOWHERE.net> writes:
>On 01/26/2016 06:31 AM, Jess Goodman wrote:
>> On Sunday, January 24, 2016 at 3:40:18 PM UTC-5, gcorn... at charter.net wrote:
>>> gcornelius at charter.net wrote:
>>>> gcornelius at charter.net wrote:
>>>>> The rest is of course stolen from you.
>>>
>>> Except the part where I forgot the parentheses
>>> about istat.and.1 in the if statement.
>>>
>>> I believe the simplified form
>>>
>>> 	if (istat.and.1)  ! no .eq.1
>>>
>>> would work, though, so no need to have compared
>>> the results of the .and. to 1.
>>>
>>> George
>
>> Actually in VMS Fortran (and in DCL) only the low-order bit of a
>>logical value determines if it is TRUE or FALSE.  I remember this
>> as "truth is odd".  And since for VMS status values "success is
>> odd" you can code this way:
>
>And I code that way in DCL. In Fortran, which is
>a standards-based language, I have begun to think
>that even if it is low bit only it is best to make
>it explicit.

Then wouldn't be be more "explicit) with...

        INCLUDE '($STSDEF)'

        if (istat.and.STS$M_SUCCESS)

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