[Info-vax] Three boot camp sessions on YouTube

[John Reagan]

On Wednesday, October 12, 2016 at 9:40:46 AM UTC-4, Bob Koehler wrote:
> In article <e5edf4ce-52e0-4622-a2ad-dd16a71f37ac>, Neil Rieck <> writes:
> > 
> > For me, the big difference between Alpha and Itanium in those videos was th=
> > e register count (32 vs. 128).  Having 128 registers may have seemed like a=
> >  good idea when they were designing that chip, but we all know that an OS i=
> > s going to require some/all those registers to be periodically saved then r=
> > estored (well, not all on every interrupt). I wonder if Intel would have im=
> > plemented 128 had they known that dynamic memory technology would keep impr=
> > oving as it has.=20
> 
>    It's been quite a few years since some chips started employing register
>    sets, where swapping context doesn't mean dumping registers to RAM, just
>    switching sets inside the CPU.  Don't know if any of the Intel
>    offerings do this, but if not, then it's probably onlhy a matter of
>    time.

Skylake has an out-of-order window of 224 instructions; 72 in-flight loads; 56 in-flight stores; 97 scheduler entries; 180 integer registers; 168 floating registers.