[Info-vax] [OT] Portable operating systems, was: Re: PowerX Roadmap -

Chris Scheers chris at applied-synergy.com
Thu Sep 22 18:43:12 EDT 2016


GreyCloud wrote:
> On 09/20/16 04:48, Johnny Billquist wrote:
>> On 2016-09-19 21:51, GreyCloud wrote:
>>> On 09/19/16 08:34, Dirk Munk wrote:
>>
>>>> Intel did design the 4-mode setup, they just made an error in the
>>>> design. Instead of correcting the design, they crippled it even more.
>>>>
>>>> I don't know if AMD has the same problem.
>>>
>>> An interesting point you just brought up. AMD right now isn't exactly
>>> getting rich these days selling their current processors. Assuming one
>>> can, approach AMD with this particular question and see what is there.
>>> If AMD did it correctly, this may give AMD some hope of increasing sales
>>> in this particular arena.
>>
>> Nope. Totally pointless. People (comapnies) in general will not write
>> any code or OS that would only work specifically on AMD processors. If
>> AMD haven't already done the same as Intel, they will. Anything else
>> just don't make sense.
>>
>> And you really do not need 4 modes. I have said that for years around
>> here. Seems like VSI understood, but a lot of people still seem to want
>> to hang on to this like a religion.
>>
> 
> Not totally true on the modes.  Why did Data Generals machines have 8 
> modes?
> I know they went out of business, but why 8?


I assume you are referring to the DG MV (32 bit) machines.

The MVs only had two modes: privileged and unprivileged.

If the ATU was switched on, there were 8 rings.  In many ways, these are 
similar to the Intel SGX design.

Code running in ring 0 was privileged.  Code in other rings was 
unprivileged.

AOS/VS only used 3 of the rings (0, 1, 7).  Other products could be 
loaded into other rings to provide services to user programs in a 
protected way.  (For example, a database.)

Since the ring indicator was part of the virtual address, I assume that 
8 rings was chosen as a balance between providing enough rings and not 
unnecessarily restricting the memory size of each ring.

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Chris Scheers, Applied Synergy, Inc.

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