[Info-vax] Intel x86-64 Processor Design Security Vulnerability?

[Simon Clubley]

On 2018-01-04, johnwallace4 at yahoo.co.uk <johnwallace4 at yahoo.co.uk> wrote:
>
> The document I looked at on the ARM website seem to 
> suggest that the critical factor in their situation 
> is whether the (un)protected data is kept in an 
> address space marked as cacheable. 
>
> Anyone who's done low level stuff like understanding 
> SMP/multi-core system synchronisation will understand 
> this concept. Even anyone who's written device
> interfaces where data can change asynchronously.
>

ARM actually did a reworking of their caching subsystem during
the ARMv5 to ARMv6/ARMv7 transition. I do remember that the
ARMv7 stuff was more faffy than the ARMv5 stuff so I wonder
if any potential weaknesses were introduced at that point.

BTW, I don't know if its changed in recent versions of the ARM
architecture, but back then you couldn't actually turn on data
caching on ARM MCUs unless you had the MMU enabled.

Simon.

-- 
Simon Clubley, clubley at remove_me.eisner.decus.org-Earth.UFP
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