[Info-vax] Intel junk...Kernel-memory-leaking Intel processor design flaw forces Linux, Windows redesign

[Simon Clubley]

On 2018-01-06, johnwallace4 at yahoo.co.uk <johnwallace4 at yahoo.co.uk> wrote:
>
> Going back a decade or four, some readers may remember 
> devices whose state changed when the device was read 
> e.g. some Control and Status Registers would clear a 
> "data available" bit if a particular device register 
> was read. 
>
> That change of device state was a "side effect" which
> would have been a Bad Thing if a speculative read had 
> got as far as a real-world device. But most "modern" 
> computers don't have that particular challenge with 
> CSRs, in part because memory has different (predictable) 
> behaviour; whatever you write into memory, you get 
> the same back. Otherwise it's not memory. OK there 
> might sometimes be side effects, and misunderstandings,
> and that's where all this fun starts.
>

That still happens with some ARM MCUs, for example, when reading
the register which contains the highest priority pending interrupt.

The standard solutions apply to I/O register access in general:

If you are using a MMU, the device registers are marked as I/O space
so hardware caching is not involved.

In addition, if you are using a HLL to actually access the register,
the register is marked as volatile so the compiler doesn't try to
get clever.

Simon.

-- 
Simon Clubley, clubley at remove_me.eisner.decus.org-Earth.UFP
Microsoft: Bringing you 1980s technology to a 21st century world