[Info-vax] Continued development of PDP-10 architecture [was Re: Hard links on VMS ODS5 disks]

[gah4]

On Sunday, July 30, 2023 at 11:28:32 PM UTC-7, terry-... at glaver.org wrote:

(snip)

> The Dolphin (KM-10 or KXF10 at various times) had hopes of being both a 
> KL-10 and a VAX: "Dolphin is an advanced computer system based on a new 
> generation CPU incorporating Macro Cell Array technology. It is the logical 
> successor to the KL-10 based PDP-10/20 system, and may well become the 
> high-end VAX system." That seems like an odd idea - the additional 4 bits in 
> registers, data paths and main memory would seem to be an unnecessary 
> expense in VAX mode. 
 
Having all instructions the same length, like most RISC systems, makes
it very easy to design pipelined parallel processors.

VAX seems to be designed very well to be hard to pipeline.

IBM S/360 and successors have three instruction lengths, all known
from the first byte.  Slightly harder, but not all that hard.

VAX, with addressing mode bytes, is well designed for serial processing,
going one byte at a time and decoding it.  Each addressing mode byte
indicates how many operand bytes it needs, and so where to find the
next addressing mode byte.

It would have been a very easy change to VAX to put all the address
mode bytes immediately after the opcode.  It is still slightly more
complicated due to indexed mode, but not all that hard. 
You get all the address mode bytes in parallel, then process any
index mode bytes, and you know where the next instruction is.

But no, for VAX you process each address mode byte, which tells
you were the next one is, which then tells where the next one is ...
Nice for serial microprograms, not for pipelining.

Well, VAX might also be designed to make it easier for assembly
programming, and especially debugging from core dumps.
I don't believe that moving the bytes around would have changed
that much, though. 

Seems like the extra bits in the word are not the worst problem.