[Info-vax] HPE Integrity emulator

[Dave Froble]

On 2/29/2024 3:39 AM, John Dallman wrote:
> In article <uroeg8$b8$1 at panix2.panix.com>, kludge at panix.com (Scott Dorsey)
> wrote:
>
>> Well, that's sort of the thing.  MAYBE the Itanium might actually
>> have been a viable architecture if the compilers could have been
>> made smart enough.  But this turned out to be a whole lot harder
>> than the Intel crew expected.
>
> No, it couldn't. The problem is the delays in accessing memory.
>
> EPIC requires the compilers to issue speculative loads far enough in
> advance to keep the processor from stalling waiting for memory for most
> of the time. However, that doesn't work: the information isn't available
> enough of the time. The compiler also doesn't know what's in what level
> of cache, because it's /impossible/ to know that when code is running on
> a multi-tasking OS that is taking interrupts.
>
> Out-of-order execution, as used on modern x86 processors (and ARM, POWER,
> IBM Z, and anything else that's still competitive) deals with the memory
> and cache problems by letting the data dependencies for instructions be
> resolved dynamically as data arrives. This works much better.
>
> EPIC only made sense in a system that was running a single process and
> taking few, if any, interrupts. That was how early embedded systems,
> which were Intel's original market, worked in the 1970s and early 1980s.
> Trying to apply that to a processor that appeared in 2001 was a massive
> failure of concept and project management. Itanium was obsolete when it
> shipped.
>
> John
>

In case we're looking for "blame", remember that EPIC wasn't Intel's brain fart, 
it came from HP, who somehow got Intel to adopt it.  You are correct, EPIC was 
shown to be a poor choice before it even shipped.  But someone(s) were too 
stubborn to listen to their own people.

-- 
David Froble                       Tel: 724-529-0450
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