[Info-vax] writing a lock free linked list

[John Reagan]

>
> 3) I am using __CMP_SWAP_QUAD, but there are also __CMP_SWAP_QUAD_ACQ
> and
> __CMP_SWAP_QUAD_REL routines.  What do those do?
>

They correspond to the 'cmpxchg.rel' and 'cmpxchg.acq' forms of the 
'cmpxchg' instruction.

Since you asked about memory barriers, I'd read up on the memory ordering 
rules for Itanium in architecture manuals.  There are sections on Vol 1 
(read 4.4.6 and 4.4.7) and Vol 2 (read 2.1) about memory ordering and the 
instructions are listed in Vol 3.

http://www.intel.com/design/itanium/manuals/iiasdmanual.htm

John