[Info-vax] Poulson info from Dave Cantor

[John Reagan]

"H Vlems" <hvlems at freenet.de> wrote in message 
news:abbe7349-7bf9-47ec-af88-346835b19a50 at v19g2000yqa.googlegroups.com...
> On 17 nov, 19:54, "John Reagan" <johnrrea... at earthlink.net> wrote:
>> http://www.realworldtech.com/page.cfm?ArticleID=RWT111710021604
>>
>> John
>
> John,  the article mentions the relationship between hardware
> performance and compiler design.
> Assuming that the two options mentioned in the article are true, what
> would that change for your compilers?

They are not MY compilers.   There are email addresses in the PPT slides 
that Tim posted.  Ask them.

> The author writes: "Itanium relies on compilers to aggressively
> schedule instructions for parallel execution into bundles."
> What does "...aggressivively schedule..." mean in terms of compiler
> design ?
> Hans

To get good execution on Itanium, a compiler needs to analyze the code to 
figure out which things can be done in parallel or not.  It is then upto the 
compiler to organize those in bundles according to the bundle type (which 
only provides certain permutations).

I suspect that code that runs today will run just fine in the future, but 
assumes that code that "runs" today isn't technically illegal.  Remember the 
situation with certain operations inside Alpha load-locked/store-conditional 
sequences?  They "worked" in early Alphas, but newer Alphas caught them.  We 
fixed the compilers but there was the worry that old .OBJs and .EXEs still 
are out there.  Thats where the CHECK_SRM tool (or whatever its name is) 
came from.  It lets you scan existing .EXEs to see if they have the bad 
seqeunces.

If what the description says is true in that the chip can do more at once, a 
compiler that 'gave up' after finding just a few parallel operations would 
want to try harder to use the new additional resources.

John