[Info-vax] Poulson at hot-chips 2011

[glen herrmannsfeldt]

David Kanter <dkanter at gmail.com> wrote:

(snip)
> Either way, Poulson isn't really an out-of-order chip - at best it
> might issue one or two instructions in slightly different order.
> However, it's still very fundamentally in-order...just a much more
> efficient approach.

Probably oversimplifying, but for VILW, even more than RISC, the
idea is that the compiler orders the instructions as appropriate.

Out-of-order was needed in the CISC days, especially with programs
optimized for slower CPUs.  The IBM 360/91 being one of the early
out-of-order processors, had to be able to run code written to
run on any S/360 model.  Among other complications, self-modifying
code is allowed.  (I believe it still is.)  The 360/91 can detect
instructions that are modified after fetch and correct the pipeline
as necessary.  Not having virtual memory to worry about, out of
order isn't so much of a problem.  Even so, imprecise interrupts,
where the PSW at interrupt might be many instructions later than
the offending instruction, make programming fun.

But I suppose no matter how you schedule you can't plan for
memory system delay.  

-- glen