[Info-vax] Poulson at hot-chips 2011

[JF Mezei]

David Kanter wrote:
>
> With replay, it works differently.  The instructions are issued -
> whether or not all the inputs are ready.  If there was a problem (e.g.
> an input wasn't ready), the instruction basically gets sent back to
> the front of the line for issue (or replayed). 


But in an EPIC design, if you have a load from memory to register
operation, followed by some addition that uses that register as input,
isn't the job of the compiler to do the load in one instruction block
and the addition in a separate block to ensure the 2 are sequentially
executed ?

Or does Poulson now ignore  those block separators and have logic to
detect dependencies, as would an out of order CPU ? And if it has such
logic, why not detect this while in the pipeline instead of at the CPU
itself ?