[Info-vax] Intel previews new Itanium "Poulson" processor

[Jan-Erik Soderholm]

John Wallace wrote 2011-02-25 00:06:
> On Feb 24, 8:34 pm, JF Mezei<jfmezei.spam... at vaxination.ca>  wrote:
>> Rich Jordan wrote:
>>> http://tinyurl.com/6ch9wj5   (hothardware.com)
>>
>> What does "Intel previews Poulson" actually mean ?
>>
>> Are they just releasing general specs and they have yet to implement all
>> of that ?
>>
>> Or have they already built sample chips that seem to work ?
>>
>> In other words, are we talking months or years before this makes it into
>>   customers' machines ?
>>
>> Also, just so I understand correctly. If they have 12 instead of 6
>> execution units, is it correct to state that a program compiled for
>> Tukwila, will still use only 6 units on Poulson, leaving the remaining 6
>> iddle ?
>
> "a program compiled for Tukwila, will still use only 6 units on
> Poulson, leaving the remaining 6 iddle ?"
>
> That was the general EPIC principle. The compiler must see the
> parallelizable stuff in a given block of code and construct bundles of
> instructions accordingly. If the execution environment widens, a
> recompile with the matching new compiler will be needed to make use of
> the VVLIW capabilities (previously IA64 was a Very Long Instruction
> Word, now it's a VVLIW). Some reports are quoting Intel as saying that
> users should not have to recompile to take advantage of the 12-
> instruction issue, which is a rather strange thing to say about
> different generations of EPIC machines and compilers.
>
> Subject to confirmation or correction by someone who really knows
> about EPIC and compilers, obviously.
>
> Far more details on superscalar vs EPIC than I can recite can still be
> found in the Alpha vs IA64 whitepaper which can still be found at:
> http://www.cs.trinity.edu/~mlewis/CSCI3294-F01/Papers/alpha_ia64.pdf
>
> On a slightly different tack, IA64 implementations have been, and
> still are, basically big fat on-chip caches with a weird processor (or
> several weird processors) attached. In the case of Poulson, the
> advertised performance is delivered by implementing some 50MB of
> cache, mostly L3 (obviously), and if you see a picture of the chip
> you'll see the cache takes up about the same space as the processing
> (unlike say a modern AMD64 chip with rather less cache).
>
> Depending on whose reports you believe, the old old story (never
> backed up by much real evidence that I saw) about "improved RAS with
> Itanium" is back again with Poulson too. If anyone out there now has
> any hard evidence of Poulson's RAS features not available in modern
> AMD64 implementations and their Intel x86-64 clones, Intel's IA64
> people (and me) would be delighted for you to share it. On the other
> hand I'd also be interested in anyone from Intel saying "it's just the
> same as Xeon really". They can't have it both ways.

First, it's 4 -> 8 *cores*. So each CPU will behave as double the amount
a "CPUs" as seen by e.g OpenVMS. That is, the scheduler has more "CPUs"
to schedule process amongst. That in itself will of course make more
jobb to be done, not by a single process but by the system as a whole.

Than there is a change in what is called "doubled execution width".
That is, as I understand it, something the compilers have to "learn"
to take advantage of. It's about how the individual instructions
are boundled.