[Info-vax] VMS port to x86

[John Wallace]

On Mar 22, 3:24 pm, Bob Gezelter <gezel... at rlgsc.com> wrote:
> On Wednesday, March 21, 2012 6:49:21 PM UTC-4, (unknown) wrote:
> > In article <GfGdnWMIE92bq_fSnZ2dnUVZ_jadn... at earthlink.com>, "John Reagan" <johnrrea... at earthlink.net> writes:
>
> > >> I wonder if INSQxIs will work on x86! :D ;)
>
> > >I'll have to ask Hoff. :)
>
> > Now it's beginning to all make sense.
>
> > --
> > VAXman- A Bored Certified VMS Kernel Mode Hacker    VAXman(at)TMESIS(dot)ORG
>
> > Well I speak to machines with the voice of humanity.
>
> VAXman,
>
> I have not worked out the precise sequences, but IMHO the x86 certainly has the ISP (Instruction Set Processor) functionality to implement the INSQxIs instructions.
>
> The original VAX implementation in microcode represented a reasonable decision reflecting the state of semiconductor technology ala 1977. The tradeoffs are different now, in favor of software implementations. The proof of this in any Computer Science text on architecture. All that is REQUIRED for multiprocessor synch is in effect a Test-and-Set (or Fetch-and-Add) primitive. Everything else can be constructed using that as a base.
>
> - Bob Gezelter,http://www.rlgsc.com


Bob,

I suspect you know better than that (you even said "in effect") but
here's a footnote or two for anyone who's interested.

1) It's not just for multiprocessor synch even though MP synch is the
classically quoted example. Unless I'm mistaken, it's also for
protecting any multi stage operation which is at risk of delivering
undesirable results if interrupted - for example, accessing a multi-
word datum in mainline code while some other bit of code in an ISR (or
in an AST, or in a different thread, or ...) might want to read (or
write) it and might get to run.

2) RISC processors tend not to use Test and Set because they tend to
have load/operate/store designs where only the loads and stores can
access memory and most opcodes only do registers. So on Alpha (and
iirc on ARM) and various others the same result is achieved using load-
locked/store-conditional instruction groups (or some equivalent with a
different name). It's written up in lots of places, for Alpha
including the VMS Programming Concepts manual or the freely
downloadable Alpha Architecture Handbook.

Every mainstream processor I know has this kind of capability one way
or another but I'm also aware of one obscure one that doesn't. On that
one you have to be careful about when non-atomic data can be accessed.
Great fun.

There is also a case to be made that these things can be done without
any underlying semaphore capability (semaphore is what T+S etc
provides) but it seems a fairly pointless argument in general.