[Info-vax] VMS port to x86

[glen herrmannsfeldt]

John Wallace <johnwallace4 at yahoo.co.uk> wrote:

(snip)
> I suspect you know better than that (you even said "in effect") but
> here's a footnote or two for anyone who's interested.

> 1) It's not just for multiprocessor synch even though MP synch is the
> classically quoted example. Unless I'm mistaken, it's also for
> protecting any multi stage operation which is at risk of delivering
> undesirable results if interrupted - for example, accessing a multi-
> word datum in mainline code while some other bit of code in an ISR (or
> in an AST, or in a different thread, or ...) might want to read (or
> write) it and might get to run.

(snip on RISC processors and store conditional)

> Every mainstream processor I know has this kind of capability one way
> or another but I'm also aware of one obscure one that doesn't. On that
> one you have to be careful about when non-atomic data can be accessed.
> Great fun.

In the core memory days, where core has a destructive read and so
requires a write back, there were some processors that would do a
read-modify-write by delaying the write back to core. (That assumes
that there are read-modify-write instructions.) 

DRAM also requires a write back, and I beleive that some early DRAM
users at least thought about delaying the write back. 

> There is also a case to be made that these things can be done without
> any underlying semaphore capability (semaphore is what T+S etc
> provides) but it seems a fairly pointless argument in general.

IBM S/360 has TS (test and set), where S/370 added CS and CDS 
(compare and swap, compare double and swap). There is some discussion
about the need to add new instructions without multiprocessing, but
that when they were shown to be needed even with a single processor
(in the case of interrupts), then they were allowed to be added.

-- glen