[Info-vax] Reimplementing VMS, was: Re: HP adds OpenVMS Mature Product Support beyond the end of Standard Support

[johnwallace4 at yahoo.co.uk]

On Tuesday, 4 February 2014 18:45:38 UTC, JF Mezei  wrote:
> On 14-02-04 10:32, Stephen Hoffman wrote:
> 
> 
> 
> > While QPI definitely helps when you're scaling past one socket, VMS 
> 
> > already has support for NUMA box designs, and that'll be useful even 
> 
> > with QPI.
> 
> 
> 
> I was under the impression that NUMA support didn't make it to Itanium
> 
> version. I take it that the "common source" between Alpha and Itanium
> 
> means that the code is still there, but just #IFDEF out when compiled on
> 
> IA64 ?
> 
> 
> 
> For the sake of discussion, say an Alpha system were built with 4 chips
> 
> of 4cores each, and Quickpath memory. (Alpha never supported dual core,
> 
> so not sure if the Alpha version of VMS has multi core support)
> 
> 
> 
> In the Galaxy/Wildfire class machines, there were separate memory banks,
> 
> with a "slow" interconnect. So each CPU block had its own "near" memory.
> 
> So it made sense to have system management tools to load processes on
> 
> specific CPUs, allocate their memory on the "near" RAM, and install
> 
> shareable imaged on near RAM too.
> 
> 
> 
> But in the case of Quickpath modern implementations, aren't systems
> 
> built with multiple paths into one memory bank ?  or is it still a
> 
> design where each CPU chip would controls a part of total memory (which
> 
> would be "near" to it) and have to Quickpath via another chip to get to
> 
> "far" memory controlled by another ?

Not sure if this has been answered, it caught my eye late yesterday and I
didn't have time...

AIUI, Quickpath is fundamentally a high speed inter-chip (inter-socket)
IO bus.

Local memory for each chip/socket isn't on Quickpath, it's on a dedicated
local memory bus.

In a multi-socket system the design may well be such that each chip has
both its dedicated low-latency local memory, and access to other sockets'
memory (at somewhat higher latency) via Quickpath.

More at e.g. http://en.wikipedia.org/wiki/Intel_QuickPath_Interconnect (and
its references).

This may sound familiar.

Does that clarify or change anything?