[Info-vax] VSI OpenVMS Alpha V8.4-2L1 Layered Product Subset Available

[John Reagan]

On Wednesday, July 12, 2017 at 9:48:48 AM UTC-4, johnso... at gmail.com wrote:
> On Sunday, July 9, 2017 at 7:04:48 PM UTC-4, clair... at vmssoftware.com wrote:
> 
> > We did not create special versions of the compilers. We just did a 
> > build with C, MACRO, and BLISS using the architecture-specific switches.
> > This was for the entire operating system build, not just selected pieces.
> 
> Does a similar opportunity exist with the Itanium build of VMS?

Not really.  The Itanium instruction set has been mostly stable since McKinley until now.  There have been a few additions of control registers plus a 'hint' instruction to help the scheduler with the hyper-threading on the chip.  Itanium has had 1-byte and 2-byte memory fetches/stores from the beginning.

The i4's did add a few additional instructions (like a 32-bit integer multiply) but the compilers are unaware of them.

The Itanium compilers will actually swallow things like /ARCH=EV6 without any message in an effort for "recompile and go".

And before anybody asks, I suspect we'll have some keywords for /ARCH for x86 to enable/disable things like SSE, etc. We aren't quite to the point to finalize the list however.