[Info-vax] x86-64 data aligment / faulting

[Stephen Hoffman]

On 2022-02-25 22:23:39 +0000, Mark Daniel said:

> Alpha and Itanium had data alignment requirements with penalties for 
> faulting.  Does x86-64?  Is sys$start_align_fault_report() et al. still 
> relevant?

I suspect the VSI answer will be "It depends". Some instruction subsets 
can either greatly benefit from or require alignment. Others, not so 
much. With recent processor generations, alignment is not so much of an 
issue, save for how much cache it might use.

VSI will be using llvm code generation for the foreseeable future too, 
which mostly-avoids dealing with this for compiled code. A lot of folks 
have looked at that code generation. At least until VSI has ~finished 
the port, and starts profiling VSI and app code, that is.

"On the Sandy Bridge, there is no performance penalty for reading or 
writing misaligned memory operands, except for the fact that it uses 
more cache banks so that the risk of cache conflicts is higher when the 
operand is misaligned. Store-to-load forwarding also works with 
misaligned operands in most cases."

Page table swappage will be interesting to profile, as OpenVMS has 
~twice the usual number of tables in use with the four-mode "emulation" 
work.

Some related reading...

https://www.agner.org/optimize/
https://www.agner.org/forum/viewtopic.php?f=1&t=75&sid=9aec4d9491a7ec1f7d01e971651c13be 

https://pzemtsov.github.io/2016/11/06/bug-story-alignment-on-x86.html
https://community.intel.com/t5/Software-Tuning-Performance/Why-should-data-be-aligned-to-16-bytes-for-SSE-instructions/m-p/1164004 

https://lemire.me/blog/2012/05/31/data-alignment-for-speed-myth-or-reality/

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