[Info-vax] x86-64 data aligment / faulting
gah4
gah4 at u.washington.edu
Mon Feb 28 18:39:55 EST 2022
On Monday, February 28, 2022 at 7:43:21 AM UTC-8, Hein RMS van den Heuvel wrote:
> On Sunday, February 27, 2022 at 3:16:43 PM UTC-5, gah4 wrote:
> :
> > As well as I remember it, Alpha only has 32 bit and 64 bit aligned
> > load/store instructions. If you want something else, you do it with
> > some other instructions. Shifts and such.
> >
> > If the compiler does all that for you, it will be pretty slow.
> Pretty slow is subjective of course. but really it wasn't too bad imho.
> As long as the compiler exactly what to expect unaligned it fetched a larger aligned chunk, mask and shift as needed and onwards.
(snip)
> Now if the compiler did not know or rather was mis-informed (about a dynamic data structure address) then an alignment trap would execute and thousands of instructions would execute some of them with system wide serialization. Ouch.
Fortunately, Fortran now allows for padding, such that COMMON variables can be aligned.
In the olden days, I believe before Fortran 90, padding wasn't allowed.
People then learned to arrange variables appropriately, with double precision
variables, usually with the strictest alignment, first.
Since you could take a COMMON array (where the compiler should know its alignment)
and pass it to a subroutine, where it wasn't known, that could happen.
I first learned about this on the IBM 360/91, which doesn't have the ability to fix them
at run time. Because of the pipelining, and especially out-of-order retirement, it doesn't
have the address where the alignment exception occurred. Other S/360 models could
fix it up, though slowly, processing the exception.
One that was a problem for some years, was that the 8087, with a 16 bit bus,
only needed 16 bit alignment. Then the 80486 could use 4 byte alignment,
and compilers (and linkers) supplied that. When Pentium was much slower
with misaligned 8 byte operands (that is, x87 double precision), it took some
years for compilers to adjust.
But since many RISC processors require alignment, people should be used
to it by now.
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